entity productReg_tb is
end entity;

architecture TESTBENCH of productReg_tb is

component productReg is
	port (
		H_in, L_in : in bit_vector(31 downto 0);
		clk, clr, H_load, L_load, hold : in bit;
		H_out, L_out : out bit_vector(31 downto 0);
		a_1 : out bit
	);
end component;

for all : productReg use entity work.productReg(STRUCTURAL);

signal high_input, low_input, high_output, low_output : bit_vector (31 downto 0);
signal clock, load_H, load_L, a_1 : bit;
signal clear, hold : bit := '0';

begin

SR64 : productReg port map (high_input, low_input, clock, clear, load_H, load_L, hold, high_output, low_output, a_1);

high_input <= "01010101010101010101010101010101" after 100 ns, "00000000000000000100000000000000" after 200 ns;
low_input <= "00000000000000000100000000000000" after 100 ns, "01010101010101010101010101010101" after 200 ns;
load_H <= '0' after 125 ns, '0' after 150 ns, '1' after 250 ns, '0' after 350 ns;
load_L <= '1' after 125 ns, '0' after 150 ns, '1' after 250 ns, '0' after 350 ns;
hold <=  '1' after 300 ns, '0' after 450 ns;
clear <= '1' after 500 ns;

PROCESS(clock)
	begin
	clock <= not clock after 20 ns; 
end PROCESS;

end architecture TESTBENCH;